vishay siliconix si9102 document number: 70001 s-70497-rev. h, 19-mar-07 www.vishay.com 1 3-w high-voltage switchmode regulator features ? 10 to 120 v input range ? current-mode control ? on-chip 200 v, 7 mosfet switch ? shutdown and reset ? high efficiency operation (> 80 %) ? internal start-up circuit ? internal oscillator (1 mhz) description the si9102 high-voltage switchmode regulator is a mono- lithic bic/dmos integrated circuit which contains most of the components necessary to implement a high-efficiency dc-to- dc converter up to 3 watts. it can either be operated from a low-voltage dc supply, or directly from a 10 to 120 v un- regulated dc power source. this device may be used with an appropriate transformer to implement most single-ended isolated power converter topologies (i.e., flyback and forward). the si9102 is available in both standard and lead (pb)-free 14-pin plastic dip and 20-pin plcc packages which are specified to operate over the industrial temperature range of - 40 c to 85 c. functional block diagram + - - + + - + - + - fb comp discharge osc 14 (20) 13 (18) 9 (12) 8 (11) 7 (10) 2 v ref gen r s q r s q drain source 3 (5) 5 (8) 4 (7) 11 (16) 12 (17) current-mode comparator c/l 1.2 v undervoltage reset 8.8 v 9.4 v bias current sources to internal circuits 10 (14) 1 (2) 6 (9) 2 (3) comparator error amplifier v ref v cc +v in v cc shutdown 4 v (1 %) osc out osc in -v in (body) comparator clock ( 1 / 2 f osc ) note: fi g ures in p arenthesis re p resent p in numbers for 20- p in p acka g e.
www.vishay.com 2 document number: 70001 s-70497-rev. h, 19-mar-07 vishay siliconix si9102 notes: a. device mounted with all leads soldered or welded to pc board. b. derate 6 mw/c above 25 c. c. derate 11.2 mw/c above 25 c. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings parameter limit unit voltages referenced to - v in (v cc < + v in + 0.3 v) v cc 15 v +v in 120 v ds 200 i d (peak) (note: 300 s pulse, 2 % duty cycle) 2 a i d (rms) 250 ma logic inputs (reset, shutdown , osc in) - 0.3 v to v cc + 0.3 v v linear inputs (feedback, source) - 0.3 to 7 hv pre-regulator input current (continuous) 3 ma storage temperature - 65 to 125 c operating temperature - 40 to 85 junction temperature (t j ) 150 power dissipation (package) a 14-pin plastic dip (j suffix) b 750 mw 20-pin plcc (n suffix) c 1400 thermal impedance ( ja ) 14-pin plastic dip 167 c/w 20-pin plcc 90 recommended operating range parameter limit unit voltages referenced to - v in v cc 9.5 to 13.5 v r osc 25 k to 1 m linear inputs 0 to 7 v + v in 10 to 120 v f osc 40 khz to 1 mhz digital inputs 0 to v cc specifications a parameter symbol test conditions unless otherwise specified discharge = - v in = 0 v v cc = 10 v, + v in = 48 v r bias = 390 k , r osc = 330 k limits d suffix - 40 to 85 c unit temp b min d typ c max d reference output voltage v r osc in = - v in (osc disabled) r l = 10 m room full 3.92 3.86 4.0 4.08 4.14 v output impedance e z out room 15 30 45 k short circuit current i sref v ref = - v in room 70 100 130 a temperature stability e t ref full 0.5 1.0 mv/c oscillator maximum frequency e f max r osc = 0 room 1 3 mhz initial accuracy f osc r osc = 330 k g room 80 100 120 khz r osc = 150 k g room 160 200 240 voltage stability f/f f/f = f(13.5 v) - f(9.5 v)/f(9.5 v) room 10 15 % temperature coefficient e t osc full 200 500 ppm/c
document number: 70001 s-70497-rev. h, 19-mar-07 www.vishay.com 3 vishay siliconix si9102 notes: a. refer to process option flowchart for additional information. b. room = 25 c, full = as determined by the operating temperature suffix. c. typical values are for design aid only, not guaranteed nor subject to production testing. d. the algebraic convention whereby the most negative value is a minimum and the most pos itive a maximum, is used in this data sheet. e. guaranteed by design, no t subject to production test. f. temperature coefficient of r ds(on) is 0.75 % per c, typical. g. c stray pin 8 = 5 pf. specifications a parameter symbol test conditions unless otherwise specified discharge = - v in = 0 v v cc = 10 v, + v in = 48 v r bias = 390 k , r osc = 330 k limits d suffix - 40 to 85 c unit temp b min d typ c max d error amplifier feedback input voltage v fb fb tied to comp osc in = - v in (osc disabled) room 3.96 4.00 4.04 v input bias current i fb osc in = - v in , v fb = 4 v, osc in = - v in (osc disabled) room 25 500 na open loop voltage gain e a vol room 60 80 db unity gain bandwidth e bw room 0.7 1 mhz dynamic output impedance e z out room 1000 2000 output current i out source (v fb = 3.4 v) room - 2.0 - 1.4 ma input offset voltage v os osc in = - v in (osc disabled) room 15 40 mv output current i out sink (v fb = 4.5 v) room 0.12 0.15 ma power supply rejection psrr 9.5 v v cc 13.5 v room 50 70 db current limit threshold voltage v source r l = 100 from drain to v cc v fb = 0 v room 1.0 1.2 1.4 v delay to output e t d r l = 100 from drain to v cc v source = 1.5 v, see figure 1 room 100 200 ns pre-regulator/start-up input voltage + v in i in = 10 a room 120 v input leakage current + i in v cc 10 v room 10 a pre-regulator start-up current i start pulse width 300 s, v cc = 7 v room 8 15 ma v cc pre-regulator turn-off threshold voltage v reg i pre-regulator = 10 a room 7.8 9.4 9.7 v undervoltage lockout v uvlo r l = 100 from drain to v cc see detailed description room 7.0 8.8 9.2 v reg , - v uvlo v delta room 0.3 0.6 supply supply current i cc room 0.45 0.6 1.0 ma bias current i bias room 10 15 20 a logic shutdown delay e t sd v source = - v in , see figure 2 room 50 100 ns shutdown pulse width e t sw see figure 3 room 50 reset pulse width e t rw room 50 latching pulse width e shutdown and reset low t lw room 25 input low voltage v il room 2.0 v input high voltage v ih room 8.0 input current input voltage high i ih v in = 10 v room 1 5 a input current input voltage low i il v in = 0 v room - 35 - 25 mosfet switch breakdown voltage v br(dss) i drain = 100 a full 200 220 v drain-source on resistance f r ds(on) i drain = 100 ma room 7 drain off leakage current i dss v drain = 100 v room 5 10 a drain capacitance c ds room 35 pf
www.vishay.com 4 document number: 70001 s-70497-rev. h, 19-mar-07 vishay siliconix si9102 timing waveforms typical characteristics figure 1. drain source 0 0 v cc - 10 % 1.5 v - 50 % t d t r 10 ns figure 2. drain 0 0 - v cc v cc - shutdown 10 % 50 % t f 10 ns t sd figure 3. 0 - reset 0 - v cc v cc shutdown 50 % 50 % 50 % 50 % t sw t lw t rw t r , t f 10 ns 50 % figure 4. + v in vs. + i in at start-up v cc = - v in +v (v) 140 120 100 80 60 40 20 0 10 15 2 0 +i in (ma) in figure 5. output switching frequency vs. oscillator resistance (hz) 1 m 10 k 100 k 10 k 100 k 1 m f out r osc - oscillator resistance ( )
document number: 70001 s-70497-rev. h, 19-mar-07 www.vishay.com 5 vishay siliconix si9102 pin configurations detail description pre-regulator/start-up section due to the low quiescent curr ent requirement of the si9102 control circuitry, bias power can be supplied from the unreg- ulated input power source, from an external regulated low- voltage supply, or from an auxiliary "bootstrap" winding on the output inductor or transformer. when power is first applied during start-up, + v in will draw a constant current. the magnitude of this current is determined by a high-voltage depletion mosfet device which is con- nected between + v in and v cc . this start-up circuitry pro- vides initial power to the ic by charging an external bypass capacitance connected to the v cc pin. the constant current is disabled when v cc exceeds 9.4 v. if v cc is not forced to exceed the 9.4 v threshold, then v cc will be regulated to a nominal value of 9.4 v by the pre-regulator circuit. as the supply voltage rises toward the normal operating con- ditions, an internal undervoltage (uv) lockout circuit keeps the output mosfet disabled until v cc exceeds the under- voltage lockout threshold (typically 8.8 v). this guarantees that the control logic will be fu nctioning properly and that suf- ficient gate drive voltage is available before the mosfet turns on. the design of the ic is such that the undervoltage lockout threshold will not exceed the pre-regulator turn-off voltage. power dissipation can be minimized by providing an external power source to v cc such that the constant current source is always disabled. note: during start-up or when v cc drops below 9.4 v the start-up circuit is capable of sourcing up to 20 ma. this may lead to a high level of power dissipation in the ic (for a 48 v input, approximately 1 w). excessive start-up time caused by external loading of the v cc supply can result in device damage. figure 4 gives the typical pre-regulator current at start-up as a function of input voltage. pdip-14 1 2 3 4 5 6 7 14 13 12 11 10 9 8 top view plcc-20 14 15 16 17 18 8 7 6 5 4 1 2 319 20 11 10 913 12 to p view pin description function pin 14-pin dip 20-pin plcc* bias 1 2 + v in 23 drain 3 5 source 4 7 - v in 58 v cc 69 osc out 7 10 osc in 8 11 discharge 9 12 v ref 10 14 shutdown 11 16 reset 12 17 comp 13 18 fb 14 20 *pins 1, 4, 6, 13, 15, and 19 = n/c ordering information standard part number lead (pb)-free part number temperature range package si9102dj02 si9102dj02-e3 - 40 to 85 c pdip-14 si9102dn02 SI9102DN02-E3 plcc-20 si9102dn02-t1 (with tape and reel) si9102dn02-t1-e3 (with tape and reel)
www.vishay.com 6 document number: 70001 s-70497-rev. h, 19-mar-07 vishay siliconix si9102 detail description bias to properly set the bias for the si9102, a 390 k resistor should be tied from bias to - v in . this determines the mag- nitude of bias current in all of the analog sections and the pull-up current for the shutdown and reset pins. the current flowing in the bias resistor is nominally 15 a. reference section the reference section of the si9102 consists of a tempera- ture compensated buried zener and trimmable divider net- work. the output of the refe rence section is connected internally to the non-inverting input of the error amplifier. nominal reference output voltag e is 4 v. the trimming proce- dure that is used on the si9102 brings the output of the error amplifier (which is configured for unity gain during trimming) to within 1 % of 4 v. this automatically compensates for the input offset voltage in the error amplifier. the output impedance of the reference section has been purposely made high so that a low impedance external volt- age source can be used to override the internal voltage source, if desired, without otherwise altering the perfor- mance of the device. error amplifier closed-loop regulation is provided by the error amplifier, which is intended for use with "around-the-amplifier" com- pensation. a mos differential input stage provides for low input current. the noninverting input to the error amplifier (v ref ) is internally connected to the output of the reference supply and should be bypassed with a small capacitor to ground. oscillator section the oscillator consists of a ring of cmos inverters, capaci- tors, and a capacitor discharge switch. frequency is set by an external resistor between the osc in and osc out pins. (see figure 5 for details of resistor value vs. frequency.) the discharge pin should be tied to - v in for normal internal oscillator operation. a frequency divider in the logic section limits switch duty cycle to 50 % by locking the switching fre- quency to one half of the oscillator frequency. remote synchronization can be accomplished by capacitive coupling of a synchronization pulse into the osc in terminal. for a 5 v pulse amplitude and 0.5 s pulse width, typical val- ues would be 100 pf in series with 3 k to osc in. shutdown and reset shutdown and reset are intende d for overriding the output mosfet switch via external control logic. the two inputs are fed through a latch preceding the output switch. depending on the logic state of reset, shutdown can be either a latched or unlatched input. the output is off when- ever shutdown is low. by simultaneously having shut- down and reset low, the latch is set and shutdown has no effect until reset goes high. the truth table for these inputs is given in table 1. both pins have internal curr ent source pull-ups and should be left disconnected when not in use. an added feature of the current sources is the ability to connect a capacitor and an open-collector driver to the shutdown or reset pins to provide variable shutdown time. table 1. truth table for the shutdown and reset pins output switch the output switch is a 7 , 200 v lateral dmos device. like discrete mosfets, the switch contains an intrinsic body- drain diode. however, the body contact in the si9102 is con- nected internally to - v in and is independent of the source. shutdown reset output h h normal operation h normal operation (no change) l h off (not latched) l l off (latched) l off (latched, no change)
document number: 70001 s-70497-rev. h, 19-mar-07 www.vishay.com 7 vishay siliconix si9102 applications vishay siliconix maintains worldwide manufac turing capability. products ma y be manufactured at one of several qualified locatio ns. reliability data for silicon tech- nology and package reliability represent a composite of all qua lified locations. for related documents such as package/tape dra wings, part marking, and reliability data, see http://www.vishay.com/ppg?70001 . figure 6. flyback converter for double battery telecommunications power supplies gnd si9102dj 1n5819 1n5819 1n4148 1 2 3 4 5 6 78 9 10 11 12 13 14 1 2 7 8 3 4 5 6 gnd + 5 v -5 v +v in 100 h 300 h 220 f 47 f 0.022 f 240 k 0.1 f 12 k 18 k 150 k 390 k 20 f -v in (- 96 v dc ) 2 1 / 2 w 0.1 f 0.1 f 0.1 f
0.101 mm 0.004 d ? square d 1 ? square a 2 b 1 e 1 a 1 d 2 b a package information vishay siliconix document number: 72812 28-jan-04 www.vishay.com 1 plcc: 2o-lead (power ic only) millimeters inches dim min max min max a 4.20 4.57 0.165 0.180 a 1 2.29 3.04 0.090 0.120 a 2 0.51 ? 0.020 ? b 0.331 0.553 0.013 0.021 b 1 0.661 0.812 0.026 0.032 d 9.78 10.03 0.385 0.395 d 1 8.890 9.042 0.350 0.356 d 2 7.37 8.38 0.290 0.330 e 1 1.27 bsc 0.050 bsc ecn: s-40081?rev. a, 02-feb-04 dwg: 5917
e 1 e q 1 a l a 1 e 1 b b 1 s c e a d 15 max 1234567 14 13 12 11 10 9 8 package information vishay siliconix document number: 72814 28-jan-04 www.vishay.com 1 pdip: 14-lead (power ic only) millimeters inches dim min max min max a 3.81 5.08 0.150 0.200 a 1 0.38 1.27 0.015 0.050 b 0.38 0.51 0.015 0.020 b 1 0.89 1.65 0.035 0.065 c 0.20 0.30 0.008 0.012 d 17.27 19.30 0.680 0.760 e 7.62 8.26 0.300 0.325 e 1 5.59 7.11 0.220 0.280 e 1 2.29 2.79 0.090 0.110 e a 7.37 7.87 0.290 0.310 l 2.79 3.81 0.110 0.150 q 1 1.27 2.03 0.050 0.080 s 1.02 2.03 0.040 0.080 ecn: s-40081?rev. a, 02-feb-04 dwg: 5919
document number: 91 000 www.vishay.com revision: 11-mar-11 1 disclaimer legal disclaimer notice vishay all product, product specifications and data ar e subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicab le law, vishay disc laims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, incl uding without limitation specia l, consequential or incidental dama ges, and (iii) any and all impl ied warranties, including warran ties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of pro ducts for certain types of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in gene ric applications. such statements are not binding statements about the suitability of products for a partic ular application. it is the customers responsibility to validate that a particu lar product with the properties described in th e product specification is su itable for use in a particul ar application. parameters provided in datasheets an d/or specifications may vary in different applications and perfo rmance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product co uld result in person al injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk and agr ee to fully indemnify and hold vishay and it s distributors harmless from and against an y and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that vis hay or its distributor was negligent regarding the design or manufact ure of the part. please contact authorized vishay personnel t o obtain written terms and conditions regarding products designed fo r such applications. no license, express or implied, by estoppel or otherwise, to any intelle ctual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.
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